1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device, more particularly to a semiconductor device including a stacked capacitor with a dielectric film made of a high dielectric constant material, and a manufacturing method thereof.
2. Description of the Background Art
A typical DRAM (Dynamic Random Access Memory) is composed of a memory cell array area serving as a memory region in which a great amount of information is stored, and a peripheral circuit area which is required for inputting data from, and outputting data to, an exterior. The memory cell array area which occupies a relatively large part of an entire area on a semiconductor chip includes a plurality of memory cells each storing a unit information which are arranged in a matrix.
A typical memory cell is composed of one MOS (Metal Oxide Semiconductor) transistor and one capacitor connected to the MOS transistor. Such a memory cell is generally called a one-transistor one-capacitor memory cell. Because of its structural simpleness, this type of memory cell makes it easy to increase an integration density of a memory cell array. For this reason, this type of memory cell has been widely used in a DRAM having a large capacity.
As for a capacitor, there have been several types of capacitors, among which a capacitor called a stacked capacitor is included. A stacked capacitor is a type in which electrodes and a dielectric film are formed so as to extend over a field oxide film and a gate electrode of a transistor, so that the electrodes face each other in an increased area. By virtue of the foregoing features, a stacked capacitor almost certainly ensures a sufficient static capacitance even if device miniaturization advances in accordance with increase in an integration density of a semiconductor memory device. As such, with the ever increasing of an integration density of a semiconductor memory device, a stacked capacitor has been more frequently used.
In order to adapt to further advance in device miniaturization, the vertical dimension of a stacked capacitor can be increased, which ensures that electrodes face each other in a sufficient area while preventing increase in the lateral dimension of the capacitor. However, in the recent days, as an element has been miniaturized to an extremely high degree, it has been getting difficult to ensure a predetermined static capacitance by using the above-mentioned method in which a structure of the capacitor is modified. Other typical three-dimensional capacitors such as a trench capacitor and a cylindrical capacitor have been placed in a situation similar to that of the stacked capacitor.
In view of the foregoing, there has been made an attempt to employ a high dielectric constant material such as BST (barium strontium titanate) for forming a dielectric film, to increase a static capacitance of a capacitor. FIG. 17 is a sectional view of a capacitor area of a DRAM memory cell according to a background art of the present invention, in which a high dielectric constant material such as BST is employed for forming a dielectric film.
Referring to FIG. 17, a dielectric film 7 made of a high dielectric constant material is interposed between an upper electrode 8 and a lower electrode 6. The lower electrode 6 is connected to a conductive plug 4. The conductive plug 4 passes through first and second interlayer insulating films 2 and 3 formed on a semiconductor substrate 1, to be connected to a surface of the semiconductor substrate 1. Further, a third interlayer insulating film 9 is formed on the upper electrode 8. The foregoing elements form a stacked capacitor.
For the foregoing elements forming the stacked capacitor, a noble metal such as ruthenium, for example, is employed as the upper electrode 8 and the lower electrode 6, and titanium nitride, for example, which functions as a barrier metal is employed as the conductive plug 4. Also, each of the first and third interlayer insulating films 2 and 9 is made of a silicon dioxide film, for example, while the second interlayer insulating film 3 is made of a silicon nitride film, for example. The dielectric film 7 made of a high dielectric constant material such as BST is formed by a reactive sputtering process, a CVD (Chemical Vapor Deposition) process or the like.
Additionally, a transistor, an active region, an isolation region made of a silicon dioxide film, and the like are formed in the surface of the semiconductor substrate 1, though not shown. Further, an aluminum interconnect is formed above the stacked capacitor, which is also not shown.
In a capacitor of a conventional DRAM memory cell, polycrystalline silicon is employed for forming upper and lower electrodes, and a silicon dioxide film formed by thermal oxidation on silicon, a silicon nitride film formed by a CVD process, or the like, is employed for forming a dielectric film. Each of the above-mentioned films employed as the dielectric film is a silicon compound, which can be easily formed on the lower electrode made of polycrystalline silicon.
In contrast, in the stacked capacitor illustrated in FIG. 17 of the background art of the present invention, a noble metal is employed for forming the upper and lower electrodes as described above, for the following reasons. If a dielectric film made of BST, for example, is applied to the above-described conventional capacitor structure to form the dielectric film of BST on the lower electrode made of polycrystalline silicon, the polycrystalline silicon of the lower electrode which is electrochemically “base” (i.e., a base metal) will be readily oxidized due to an oxygen atom included in the BST of the dielectric film. As a result, a silicon dioxide film is formed in an interface between the dielectric film and the lower electrode. Because of a relatively low dielectric constant of the silicon dioxide film, the effects produced by employing a high dielectric constant material is nullified, to considerably reduce a static capacitance of the capacitor. Further, a resistance of the polycrystalline silicon as the lower electrode is increased. The same problems occurs in the upper electrode.
For the foregoing reasons, when a high dielectric constant material such as BST is employed for forming a dielectric film, a noble metal which is electrochemically noble and highly anti-oxidizable should be employed for forming upper and lower electrodes. Such a noble metal includes platinum, iridium, palladium or the like. That is because ruthenium is exemplarily cited as a material for the upper electrode 8 and the lower electrode 6 in the above description for the stacked capacitor illustrated in FIG. 17.
Further, the purpose of employing a material having a barrier property such as titanium nitride for forming the conductive plug 4 in the stacked capacitor illustrated in FIG. 17 is to prevent silicidation reaction between the lower electrode 6 and the semiconductor substrate 1, thereby to prevent increase of a resistance, or to prevent an oxygen atom from separating from the dielectric film 7 or the like and arriving at the semiconductor substrate 1 through the lower electrode 6, thereby to prevent the semiconductor substrate 1 from being oxidized.
As is known, it is difficult to etch a noble metal film into a desired pattern by using a photolithography technique or conventional etching techniques. Accordingly, to form a minute structure such as the lower electrode 6 illustrated in FIG. 17 by using a noble metal will involve difficulties.
Hereupon, a damascene process has been employed for patterning a noble metal film. More specifically, a mold made of a silicon dioxide film or the like which is relatively easy to etch is formed on a substrate, and an opening of a desired shape for an electrode is formed in the mold. Subsequently, a noble metal film is buried in the opening, and a surface of the buried noble metal film is planarized by a CMP (Chemical Mechanical Polishing) process or the like. Then, the mold is removed, to complete a minute electrode of the noble metal film. In a damascene process, fine processing is performed on a silicon dioxide film, which makes it easier to manufacture a device as compared with a case where fine processing is performed directly on a noble metal film.
A damascene process is applicable to the background art of the present invention illustrated in FIG. 17, in which the lower electrode 6 is formed by burying a noble metal film in an opening of a mold. At that time, a heat treatment is performed on the noble metal film in order to allow the noble metal film to keep a desired shape for an electrode. The heat treatment causes the noble metal film forming the lower electrode 6 to shrink in the opening of the mold, resulting in deformation of the lower electrode 6, to pose a problem.
FIG. 18 is another sectional view of the same stacked capacitor as illustrated in FIG. 17 for illustrating the problem mentioned above. More specifically, FIG. 18 shows a state where a noble metal film 6d buried as the lower electrode 6 in an opening of a mold 10 shrinks, so that a vacancy 10c is left between the noble metal film 6d and the conductive plug 4. It is generally considered that such a phenomenon occurs due to the heat treatment on the noble metal film 6d in which oxygen or the like contained in the noble metal film 6d is discharged in a gas phase. Accordingly, no contact can be made between the noble metal film 6d and the conductive plug 4 in the state as shown in FIG. 18, and thus the noble metal film 6d does not function as the lower electrode 6.
One conceivable solution to avoid the above-described problem is to perform a heat treatment on the noble metal film 6d after removing the mold 10. However, this would allow the noble metal film to easily shrink differently among respective portions of the noble metal film, resulting in formation of a deformed lower electrode 6e as illustrated in FIG. 19. In a state as illustrated in FIG. 19, it is likely that the lower electrode falls down or comes into contact with another lower electrode near the lower electrode, to pose another problem.
Otherwise, the vacancy 10c between the noble metal film 6d and the conductive plug 4 may not be left. Even in such a situation, however, it is probable that connection between the noble metal film 6d and the conductive plug 4 is weakened due to shrinkage of the noble metal film 6d. In this situation, there is a high possibility that the lower electrode 6 is detached from the conductive plug 4 upon vibration or impact on a finished device. The finished device has a low resistance to impact or the like.